Relational Physical Design: No Absolutes
Publication: Electronic Engineering Times (EE Times)
November 08, 2004 -- Physical design for reuse remains stuck at the hard macro, which prevents intellectual property from being optimized to the target design or easily migrated to the next process generation. By contrast, techniques for IP reuse have become commonplace in the logic design world.
Reuse became practical with the advent of logic synthesis, which separated logic function from implementation technology (i.e., a gate library). But physical design intent is captured in a technology-specific way. Floor plans are hard to reuse. Block pins, macros and the power grid are specified in hard-coded coordinates. IP implementation scripts are written for a specific tool set, specific netlist and specific cell library. And they are written quickly, and are not intended to be used again by other engineers.
By Lane Albanese. (Albanese is director of design and application engineering at ReShape, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.