Design for Volume
Publication: Chip Design Magazine
November 1, 2004 -- Design used to be an end-point for the logic designer. Once the design was complete, a standard, repeatable set of transformations that adhered to minimal design rules usually correlated to an acceptable level of silicon performance. Meanwhile, the analog people fussed over circuits and layouts until the design manager declared it was time for tape-out. At that point, analog designers had to burn the midnight oil because the structures, topology, and device characteristics all interacted-usually to the detriment of the circuit performance.
With the advent of nanometer processes, however, abstractions of digital signals and assumptions of device stability and matching seem to have gone out the window. Before fine-line processes emerged, some percentage of yield could be assumed from historic data and empirical formula to project yield as a function of defect density and processing steps. Adding in a fudge factor of some sort for wafer sort, assembly, and final-test dropouts provided for a target yield number that was usually fairly close to the theoretical process number. Today, however, a trend first seen in the 180-nanometer processes-and reinforced in the 130-nanometer node-is yield numbers which differ significantly from the expected values of earlier times.
As a result, designers are finding an increasing need to consider yield and manufacturing as functions of design. The new process nodes threaten the core assumptions of IC design, that the devices on a single chip are relatively well matched and device and process variability fall within fairly small ranges. The blurring of functions across the boundaries of design-CAD, test, manufacturing, and process node considerations-require designers have much greater access to highly accuracy data from the other sectors in the design and development teams. The increasing mix of analog and digital circuits existing side-by-side on a single chip also demands changes to the design flow, tools, methodologies, and design rules, all of which currently require significant tweaking to apply to the next process node.
By Tets Maniwa, Chip Design Magazine Editor
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.