Designing with Real Intentís Verix
Publication: Chip Design Magazine
September 1, 2004 -- The ASIC Group is a Silicon Valley based design and verification services company. In order to best serve our customers, we are continually investigating new tools and techniques to improve the ASIC design process. It was in that spirit, that we decided to evaluate the Verix property checking tool from Real Intent Corp. (Santa Clara, CA) on a live design project. We wanted to see what added value this comprehensive formal verification tool could add to our existing verification capabilities.
The particular design project we used to benchmark Verix was a redesign of an existing core developed for one of our customers. The core design team consisted of six experienced engineers from the customer and The ASIC Group combined. The project was the third generation of an existing design that already had a history of successful silicon on three different chips, and had been executed from 0.35 micron down to 0.13 micron. This newest version of the design was targeted for increased speed, decreased power and area, and increased performance.
With a design this mature and such a seasoned team of senior designers, one would think that Verix would not find many issues with the design. However, weíll describe here the bugs that were found by Verix, and detail the level of effort required to unearth them. Due to the proprietary nature of the design, mock design issues have been substituted here to illustrate our findings. In other words, the names have been changed to protect the innocent.
By James M. Lee. (Lee is the president of the ASIC Group Inc.. He is also the author of "Verilog Quickstart," now in its third edition.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.