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ESL Bridges Design and VerificationPublication: Chip Design Magazine May 1, 2004 -- At DAC 2003, industry experts discussed the "renaissance" of Electronic System-Level Design (ESL), referring back 10 years to DAC 1993 when system-level design was a hot topic as well. The pundits pointed out, however, the distinct difference between now and then. Today, it is verification that’s driving the widespread adoption of ESL technologies. There’s an obvious bridge between ESL and classical functional verification, which is the executable functional virtual prototype (FVP) at the transaction-level representing the design intent. Various techniques are available to help with the creation and verification of functional correctness of an FVP. These techniques include transaction-level modeling using SystemC, instruction and cycle accurate processor modeling for verification of an FVP in the context of embedded software, performance analysis, and interface synthesis. We will discuss all of these issues in this article and will also outline the techniques that use the FVP as a reference for verification during RTL implementation. This ensures that the function of the design representation at the RT-level remains intact in comparison to the FVP. Technologies include dynamic and static assertion-based verification, verification acceleration, and coverage-driven verification. Specific attention will be given to the leverage that the ESL representation has on RTL verification. By Frank Ghenassia, Bart Vanthournout, Frank Schirrmeister, and Shusaku Yamamoto. (Ghenassia is with STMicroelectronics, Vanthournout is with CoWare, Inc., and Schirrmeister and Yamamoto are with Cadence Design Systems, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |