ARC International Announces New Roadmap of Pre-Optimized Configurable Processor Cores

February 14, 2005 -- ARC International has announced a new roadmap for the company’s configurable processors. The ARC 600 and 700 families now include eleven configurable cores that offer pre-optimized size, speed and power characteristics to enable developers to meet specific requirements of high-growth embedded markets. Each core in the 600 and 700 families consumes significantly less silicon area and power when compared to fixed processors, and extends ARC’s processor architecture to a wider range of consumer, storage and networking applications.

Close to one hundred companies are leveraging ARC’s configurable technology to create SoCs for products such as cell phones, digital set-top boxes and portable mass storage devices. Each of these ARC-Based applications contains ARC processors that have been uniquely configured to enable developers to meet stringent requirements of the end market.

"To continue the momentum of record growth in our SoC business, we have launched completely new 600 and 700 core families that increase more than fivefold the number of processors we offer to customers," said Derek Meyer, vice president of marketing at ARC International. "Each new, pre-optimized core enables licensees with the power of ARC’s configurable technology so they can be fine-tuned for even better performance, smaller size and less power consumption."

The ARC 600 Core Family

The ARC 600 family of processor cores uses an efficient five-stage pipeline to deliver 1.3 DMIPS/MHz performance. The cores’ small size and power consumption makes them ideal for battery-operated and cost-sensitive devices, such as consumer products, automotive control, storage products and networking:

The ARC 605 Core is the one of the smallest, lowest power 32-bit CPU cores. In a 0.13 micron process, it offers a maximum clock frequency of 250 MHz, power consumption of 0.06 mW/MHz and a die size of 0.31mm2. The ARC 610D Core has the additional feature of a full performance DSP engine, which eliminates dedicated DSP logic on an ARC-Based SoC. Optimized for hard real-time processing, the 610D core has a maximum clock frequency of 260 MHz in a 0.13 micron process, power consumption of 0.07 mW/MHz and a die size of 0.64mm2. The ARC 625D Core is a general purpose CPU/DSP core with flexible memory options, which make it ideal for applications that require a real-time embedded operating system (RTOS). The 625D core has a maximum clock frequency of 240 MHz in a 0.13 micron process, power consumption of 0.08 mW/MHz and a die size of 0.71mm2.

The ARC 700 Core Family

The ARC 700 family of high performance cores uses a seven-stage pipeline to deliver 1.2 DMIPS/MHz performance. Each core has DSP capability as a standard feature with optional DSP functions in the form of the ARC XY Advanced DSP subsystem. RTOS and secure processing support is provided, as is the option for a Memory Management Unit (MMU). The 700 core family also makes an ideal platform for devices requiring embedded Linux.

The ARC 710D Core is ideal for demanding real-time tasks such as networking, storage and multi-core designs. It has a maximum clock frequency of 405 MHz in a 0.13 micron process, power consumption of 0.11 mW/MHz and a die size of 0.72mm2. The ARC 725D Core provides a high performance, general purpose solution for a wide range of applications including home entertainment, digital cameras, networking devices, laser printers and storage systems. It has a maximum clock frequency of 400 MHz in a 0.13 micron process, power consumption of 0.12 mW/MHz and a die size of 0.96mm2. The ARC 750D Core delivers best-in-class performance while remaining significantly smaller and less power-hungry than processors offered by competing companies. Target applications include advanced 3G phones, set-top boxes, wireless LANs and game consoles. The 750D core has a maximum clock frequency of 400 MHz in a 0.13 micron process, power consumption of 0.13 mW/MHz and a die size of 1.12mm2.

Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
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