What Designers Need to Know About TCAD
Publication: eeDesign (EE Times EDA News)
April 4, 2005 -- Issues with manufacturability and yield are forcing the EDA industry and IC manufacturing to move closer together. In particular, process and device information that affect functionality and yield need to be incorporated into the design technology, addressing more comprehensively issues like Design for Manufacturability (DFM) and Yield (DFY).
Currently DFM focuses mostly on optical proximity correction (OPC), neglecting other factors like process and device variability. In yield terms, this means that the current focus only covers parts of the parametric yield issues. We have to extend our coverage of DFM and redefine it.
The information needed by designers includes layout sensitivities as well as the effect of process variability on the electrical characteristics of devices and interconnects. At the 65nm node the variability will increase significantly as a result of feature scaling, and the introduction of new materials and innovative techniques such as strain engineering.
The current dilemma faced by the EDA industry is that a complete enumeration of manufacturability related rules, requiring a process and device model derived from manufacturing data, is not available until sufficient silicon has been processed. Yet most of the circuit blocks have to be designed with EDA tools before this information is available.
By Dipu Pramanik, Lars Bomholt and Wolfgang Fichtner. (Dipu Pramanik is currently Group Director of R&D in the TCAD product unit of Synopsys; Bomholt is Group Director, R&D, at the Silicon Engineering Group at Synopsys; Fichtner is VP and General Manager, TCAD Engineering, at the Silicon Engineering Group at Synopsys.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.