How FPGA Packaging Drives Signal Integrity
Publication: eeDesign (EE Times EDA News)
May 17, 2005 -- Until recently, signal integrity has been a concern relegated predominantly to multi-gigabit serial interface design. Today, it is an aspect of design that engineers building high-speed parallel interfaces like memory interfaces can no longer choose to ignore.
As speeds increase, bit periods shrink, reducing the available timing margins. Today's memory interfaces run at greater than 500Mbps per line with rise times in the hundreds of picoseconds. This creates a substantial signal integrity challenge for the FPGA designer.
As interfaces get wider and faster, simultaneously switching output noise (SSN) grows in severity. SSN adds to the system jitter, eating into the timing margin and affecting system performance. In the worst case, SSN can cross the logic threshold, causing the system to malfunction altogether.
Good package design is critical to good noise performance in FPGAs. This article describes the package design considerations with a focus on signal integrity and its impact on system performance.
By Panch Chandrasekaran. (Chandrasekaran is connectivity marketing manager at Xilinx Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.