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IP Quality is the Key to Successful SoC DesignContributor: VSI Alliance (VSIA) June 6, 2005 -- The growth of IP in silicon chips, both from third parties and internally developed, is a natural response to Moore's Law-shrinking process nodes leading to more complex system-on-a-chip (SoC) designs running at higher clock rates. By embedding pre-designed and pre-verified semiconductor IP, designers are able to keep pace, for the most part, with the complexity challenges of state-of-the-art designs. Unfortunately, IP usage has not grown as rapidly throughout the semiconductor industry as originally envisioned. One obstacle to more widespread acceptance and deployment of IP is a lack of standardization in evaluating the quality of IP cores and of IP developers. IP integrators need a standardized IP evaluation mechanism to compare similar IP cores from different sources and to access the risk involved with using a selected core in a specific chip. IP vendors also need this kind of evaluation tool to gauge the quality of their products and to adequately describe their products to perspective customers. With these needs in mind, the VSIA Alliance (VSIA) has taken on the standardization of IP quality as one of its primary goals. Now in its ninth year, the VSIA is the SoC and IP umbrella organization for the electronics industry. The Alliance's mission is to dramatically enhance the productivity of the SoC design community by providing leading-edge commercial and technical solutions, and insight into the development, integration and reuse of IP. Currently there are four "Pillars" or working groups in VSIA includingIP Protection, IP Quality, IP Infrastructure and Research & Development. Large member companies identified these pillars charters as top priorities for their companies. The IP Quality Pillar charter is to define the essential Quality Attributes of any IP core required to make it properly functional and efficiently reusable in SoCs and the Pillar has met its charter through the creation of the QIP (Quality IP) Metric. We know that IP quality is one of the biggest issues faced by both IP integrators and IP providers. By quantifiably measuring the characteristics of an IP vendor or IP core, VSIA's QIP Metric is a tool that can substantially reduce the time required when making an IP purchase decision. The Metric helps the IP vendor and IP consumer communicate based on an objective foundation. Besides setting up the basis for measuring a core's characteristics against an industry-approved list of attributes, the standard provides a view of the IP vendor's general approach to IP development. This, in turn, levels the playing field for vendors and allows an integrator to evaluate similar cores from competing vendors. The QIP Metric also provides a way for the IP vendor to showcase its products. At some point, when the QIP Metric is widely adopted and used by IP vendors and integrators, vendors will not be able to compete in the marketplace without providing a QIP Metric score with each of their cores. Still evolving, VSIA's QIP Metric is gaining acceptance by several well known IP vendors and chip developers. The latest version of the Metric will be announced at the Design Automation Conference in Anaheim, California later this month. Based on feedback from early adopters, the QIP Metric will eventually become the standard for quality evaluation of all types of IP for both vendors and integrators alike, and will help accelerate the SoC revolution. By Mike Kaskowitz, President, VSI Alliance | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |