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Bandwidth Match Avoids I/O SnarlPublication: Electronic Engineering Times (EE Times) March 3, 2003 -- "Scan is the most general and pervasive digital structural-test technique, one that has been a standard in the industry for years. However, scan-design methodologies have not improved in all that time. The traditional methodologies do not use resources for scan design efficiently, which results in suboptimal scan designs in terms of test time, test interface and test power. "Most important, the frequency of the scan I/O ports is completely ignored as a resource and is typically restricted to the frequency of the internal scan chains during test. Since the internal scan chains are typically designed to operate at a low frequency for reasons of test power and design effort, the scan frequency gets tied to a low value as well. This results in a bandwidth (pins x frequency) bottleneck across the scan interface, especially if the automated test equipment (ATE) is capable of providing higher bandwidth." By Ajay Khoche. (Khoche is DFT Scientist, Agilent Laboratories, Agilent Technologies Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |