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DFT: A Systems Technology for System ChipsPublication: Electronic Engineering Times (EE Times) March 3, 2003 -- "Recently, DFT elements have begun to show up in more and more large complex SoC devices. The concept of scan no longer raises the objections of overhead to the extent it used to. Yet, customers and vendors of DFT technology are still trying to realize the full potential of a comprehensive, structure-oriented DFT strategy as a consistent engineering interface platform. "Systems companies traditionally have been vertically integrated and, thus, have been exposed to the individual difficulties and costs as well as the combined product life cycle effects of design, manufacturing, and product maintenance decisions. Being part of one company, systems house organizations are more motivated to develop and use a common methodology throughout the design, manufacturing, and product support chains than the different players in a disaggregated supply chain." By Bernd Koenemann. (Koenemann is a Fellow, Cadence Design Systems, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |