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It’s All About the Routing, Stupid!Contributor: Pyxis Technology, Inc. October 17, 2005 -- It’s no secret that the task of designing and manufacturing today’s extremely complex multi-million gate ASICs and SoCs is becoming increasingly problematical. The message is taking hold that the design community can no longer ignore the issues of yield and manufacturability. The question in the industry has evolved from "why should my design team worry about manufacturability and yield?" to "what should my design team do about manufacturability and yield and where should I start?" Unfortunately for the designer, the industry has not yet provided a magic "knob" that designers can turn to adjust the yield of their designs. Most SoC designers have three main things they can control: the architecture of the design, the choice of building blocks they use to create the design, and the routing that hooks everything together. Redundant and self-healing architectures have already been employed in yield-sensitive circuits such as memories. When it comes to SoC designs containing large amounts of control logic and peripheral interfaces, however, these techniques can only go so far before performance and complexity issues make them too unattractive to use. To date, most DFM/DFY activities have focused on front-end-of-line (FEOL) issues – such as the patterning of poly gates, diffusion areas, and contacts – none of which are controlled by the SoC designers. Instead, these issues are currently addressed by library and IP suppliers or performed as post-processing steps once the layout portion of the design has been completed. Interestingly, there is one item the design team can control that has a big impact on the design’s performance, manufacturability, and yield, and this is how the design is routed. Routing is the only portion of an SoC design that truly can not be pre-processed before the design commences, and it can have a dramatic affect on the SoC’s final performance and yield characteristics. Unfortunately, the current strategy of post-processing a design’s interconnect is probably one of the worst things one can do to the design, especially if the designer is not involved. Most post-route processing applications today will make modifications to the routing to enhance manufacturability and yield with little or no regard to the impact these changes have on a design’s electrical characteristics. Remembering that 70% to 80% of the delay paths in an SoC are attributed to its interconnect, any changes made to the routing cannot fail to have significant impact on the design’s performance. To make matters worse, once post-processing has been performed, designers find it very difficult to bring the design back into the routing environment to fix any timing issues caused by these modifications. What the industry needs is a new closed-loop process that is flexible enough to comprehend the trade-offs of timing, signal integrity, area, printability, manufacturability, and yield. Routing is the place for the SoC designer to make these trade-offs. It is the biggest "knob" the designer can turn that will affect all of these metrics. Unfortunately, today’s routers are not up to the challenge, because they were built with a different set of constraints and problems in mind. The bottom line is that we desperately need a new generation of routing engines that natively address DFM/DFY issues and that have the "ears" to listen to manufacturing and the ability to "speak" to manufacturing. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |