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Tackling Test Challenges for Low-Power DesignPublication: eeDesign (EE Times EDA News) November 7, 2005 -- More semiconductor companies are adopting low-power design strategies that combine multiple supply voltages, voltage scaling, extensive clock gating coverage and other techniques that push performance and increase complexity of device operating modes. In turn, this growing interest in power management techniques in design dictates a growing need for increased attention to power concerns in test and greater urgency for more effective design for test (DFT) methods for low-power designs. Power has become a premium across mainstream applications ranging in diversity from battery-powered personal appliances to multiprocessor server farms. For designers, power management means controlling leakage power lost during standby mode, as well as dynamic power consumption when multiple transistors switch in unison to perform desired functions. By Chris Hawkins, Jason Doege and George Kuo. (Hawkins is a Principal Member of Technical Staff at ARM; Doege is a senior test specialist for Cadence; Kuo is technical director of Design Chain Initiatives at Cadence.) | |
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