Critical Area Optimizations Improve IC Yields
Publication: eeDesign (EE Times EDA News)
January 9, 2006 -- The move to advanced nanometer nodes and new process materials is diminishing semiconductor designersí ability to estimate and realize device yields. Yield, which has been traditionally limited only by defect density, is now impacted greatly by the interaction of process-related deviations with design elements.
In the past, random defects caused by particle contamination were the dominant reason for yield loss, and it was the foundriesí responsibility to control such defects through inspection and other techniques. Today, systematic variations, such as metal width and thickness variations or mask misalignment, are also major contributors to yield loss.
The impact of process variations on design parameters is becoming more extensive with the reduction in feature dimensions and the increasing design complexity. Reducing yield loss mechanisms has now become ever more dependent on design, not just improvement of the manufacturing process. Once an afterthought, yield is becoming a considerable concern for designers.
By Frank Lee, Atsuhiko Ikeuchi, Yoshiki Tsukiboshi, and Takashi Ban. (Lee is vice president of R&D for Synopsys; Ikeuchi is manager, System LSI Division, Toshiba Corp.; Tsukiboshi is chief specialist, EDA Technology Development Department, Toshiba Microelectronics; and Ban is specialist, EDA Technology Development Department, Toshiba Microelectronics.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.