Understanding Design for Yield
Company: Ponte Solutions, Inc.
With the move to sub-100-nm feature processes, predictions of initial yields are in the single digits. As a result, the yield that has been considered a fab-only problem is moving up into the design flow. Most of electronic design automation (EDA), manufacturing equipment and semiconductor intellectual property companies are proposing a variety of visions and solutions for design for manufacturing (DFM) and starting to talk about yield. All of these different visions and solutions can be very confusing to a designer or manufacturing engineer who is faced with the challenge of developing a solution to get chips to yield.
In this paper, we will identify the drivers of DFM as well as its limitations and will discuss the emergence of a new segment of EDA – design-for-yield (DFY). We will examine the requirements for yield-aware EDA tools and flows; present a classification of defects and failure types; introduce the concept of unified yield model; and discuss the application of models within a standard EDA design flow.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.