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FPGAs Balance Lower Power, Smaller Nodes Drip by DripPublication: EDN Magazine June 8, 2006 -- About eight years ago, just when FPGA vendors figured out how to increase the gate counts of their devices to rival those of ASICs, the market started demanding higher performance. It took the industry about four years to make these now-million-gate devices run at speeds comparable with those of ASICs. But it did so just as the market made low-power devices its top priorities. So, once again, the FPGA vendors are trying to address demand for low-power operation as they approach ever-smaller process nodes. This time, however, the task of meeting market demand is more challenging because, in making FPGAs larger and faster over the years, FPGA-chip architects squeezed more power and capacity from silicon mainly at the expense of increasing power consumption. FPGAs got most of their speed increase over the years from using thin-oxide transistors that grow thinner with every process reduction. Thinner gate oxides come with a nasty side effect: They leak power, and leakage, or static power, produces heat. Starting at the 130-nm node, static power in transistors began to explode. It got worse at 90 nm, and, if manufacturers fail to address the issue, it would get exponentially worse at 65 nm (Reference 1). By Michael Santarini, EDN Senior Editor | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |