Cadence Test and Formal Verification Technology Speed Time to Market for Matrox
July 5, 2006 -- Cadence Design Systems, Inc. today announced that Matrox Graphics, Inc. has committed its test insertion flow to Cadence Encounter Test Architect design for test (DFT), Encounter True-Time Test automatic test pattern generation (ATPG), and Encounter Conformal equivalence checker technologies. Cadence Encounter Test and Encounter Conformal Equivalence Checker are part of the Cadence Encounter digital IC design and implementation platform.
"As a strategic partner, Cadence provides Matrox a state-of-the-art and easy-to-adopt test methodology that translates directly to a competitive advantage through higher product quality and lower test cost, while Encounter Conformal technology has consistently delivered efficient and comprehensive verification from RTL to final netlist, helping speed time to market," said David Chiappini, ASIC Projects Manager at Matrox.
Matrox uses Encounter Test Architect to minimize its cost of test. Matrox employs Encounter True-Time's timing-aware delay test to detect small delay defects, commonly missed by conventional delay testing approaches that do not take design timing into account.
Encounter Conformal helped Matrox verify the functional equivalence of various netlists throughout the implementation process. Encounter Conformal also performs clock domain crossings for correct synchronization and, with equivalence checking, creates a complete verification solution to help minimize design re-spin risk.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.