ASIC Design Managers Face Gobal Challenges
Publication: EDN Magazine
October 12, 2006 -- With the emergence of IC foundries in Taiwan, Singapore, and mainland China over the last decade and an abundance of relatively inexpensive engineering resources in India, Eastern Europe, and mainland China now available, ASIC and SOC (system-on-chip) design is becoming a global effort. Indeed, it is difficult to find a company that has not established an offshore design center or is not tapping into a foreign location for some type of assistance, whether it is for manufacturing a chip at a Taiwanese fab, design services in India, or IP (intellectual-property) creation in Israel.
An abundance of global resources is available to IC companies. But that abundance brings numerous challenges that management must face in organizing ASIC- and SOC-design efforts to get chips to market on time. Global efforts require managers to negotiate different time zones, language, cultures, holiday schedules, licensing, and infrastructure. Beyond these issues, design managers are coming up with unique strategies to ensure that designs meet goals and are on time. To complete designs on time, they use localized R&D with global manufacturing, global-platform-based design, and global-design factories.
By Michael Santarini, EDN Senior Editor
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.