Handling Differential Skew in High-Speed Serial Buses
Publication: EDN Magazine
October 26, 2006 -- Until recently, wide synchronous buses were the method of choice for high-data-rate digital communications because digital logic could not support the switching rates for required bandwidth on a single lane. Unfortunately, wide synchronous buses become problematical at high clock rates. As speeds increase and buses become wider, it becomes increasingly difficult to obtain required setup-and-hold times on all the lines in a wide bus. These facts have driven the use of very-high-bit-rate serial buses with embedded clocks.
A little-regarded phenomenon, differential skew, has become a fundamental performance-limiting issue for high-speed serial-communications links. "Differential skew" refers to the time difference between the two single-ended signals in a differential pair. The operation of such links involves significant amounts of signal processing to recover clocks, reduce the effects of high-frequency losses, reduce ISI (intersymbol interference), and improve SNR. Skew limits the bandwidth of these links, adds data-dependent jitter, and limits the possibility of equalizing links to compensate for high-frequency skin effect and dielectric losses.
By Arnold Frisch. (Frisch is principal of intellectual-property vendor WarpSpeed Chips LLC.)
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