Programmable Accelerators: Hardware Performance with Software Flexibility
Publication: EE Times Signal Processing DesignLine
February 1, 2007 -- Higher product design costs and risks have been driving the electronics industry to an increased focus on developing "product platforms." The architecture often needs to be able to support new product requirements over the lifetime of the platform without a chip re-spin.
This creates conflicting requirements for the platform. On one hand, the solution needs to be customized to achieve performance and cost close to that of an ASIC. On the other hand, there is a need for the flexibility of a programmable solution, where modifications and enhancements can be done by software changes rather then by re-spins of the hardware. But what if the performance requirements are too high for an off-the-shelf processor? What if many tasks need to be executed in parallel, but cost constraints prohibit use of separate off-the-shelf processors for each task?
In this article we will present a language-based tools approach that enables the designer to: add programmability to hardware accelerators, customize programmable architectures to achieve a more than 100 times performance improvement over off-the-shelf processors, and introduce software flexibility into the design without sacrificing design productivity.
By Dr. Andrea Kroll. (Kroll is the marketing director for programmable solutions at CoWare, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.