How to Architect, Design, Implement, and Verify Low-Power Digital ICs
Publication: EE Times EDA Designline
January 29, 2007 -- In recent years, power consumption has moved to the forefront of digital integrated circuit (IC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate.
It is common to think of low-power designs only in the context of handheld, battery-powered devices such as personal digital assistants (PDAs) and cell phones. And it is certainly fair to say that this class of device is at the top of low-power development concerns. In reality, however, power consumption (and corresponding heat generation) is also of significant interest to semiconductor segments with fixed installations, such as networking, set-top boxes, and computing devices.
By Andy Eliopoulos, Pinhong Chen, and Dr. Qi Wang. (Eliopoulos is Vice President of R&D; Chen is an Engineering Director; and Wang is an Engineering Director at Cadence Design Systems, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.