Model-Based Metal Fill Optimizes Planarization and Increases Yield
Publication: EE Times EDA Designline
March 22, 2007 -- Copper interconnect was introduced to the mainstream at 130nm because of its significant advantages compared to aluminum, such as reduction in resistivity and power consumption and resistance to electromigration. Together with its advantages, copper interconnect also brought challenges to achieving high yield due to effects such as dishing, dielectric erosion and thickness variations caused by Chemical Mechanical Polishing (CMP) during planarization.
To account for copper's side effects, physical design tools insert dummy metal patterns, called metal fill, so that designs meet the required metal density " as specified by foundries " to reduce the thickness variation. However, at 65nm and below, meeting the density target does not always achieve minimum metal thickness variation, as the copper topography is affected by several layout and process parameters.
To adequately control thickness at advanced technology nodes, new techniques are necessary to take into account not only the metal density but also the metal thickness itself.
By Charles Chiang, Seiji Norimatsu and Mitsuhiro Tomita. (Chiang is a Scientist in the Advanced Technology Group at Synopsys, Inc,. and both Norimatsu and Tomitais are Researchers with STARC.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.