How Low Can You Go? A Look at 45-nm IC Design Challenges
Publication: EDN Magazine
September 13, 2007 -- The 45-nm node promises SOC (system-on-chip) designers either a 40% increase in transistor counts over 65 nm or a 40% reduction in die size, but mask costs for 45-nm processes will run, at least initially, in the multimillions of dollars. Some designers, especially those with experience designing in either the 65- or the 90-nm modes and that are familiar with low-power-design techniques, will find the transition to the 45-nm process fairly straightforward. That experience may help to alleviate some of the cost burden of the transition, according to some foundries, IDMs (integrated-device manufacturers), and EDA vendors.
With the introduction of 45-nm processing, foundries are now introducing RDRs (restrictive-design rules) for bulk-CMOS processes, mandating the use of advanced low-power-design techniques, and requiring the use of DFM (design-for-manufacturing) tools. Some foundries are also recommending that designers use probability-analysis tools, such as those for SSTA (statistical-static-timing analysis) and static statistical-power analysis to help reduce timing and power problems. Some hold that probability-analysis tools, although promising, may still be immature.
By Michael Santarini, EDN Senior Editor
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.