Sign-Off for Manufacturability
Publication: EE Times EDA Designline
October 8, 2007 -- The electronic design industry continues to push the limits of Moore's Law through smaller and smaller process nodes. As we reach 45nm, manufacturing and process control becomes increasingly difficult, making it imperative that manufacturability issues be addressed much earlier in the design cycle to avoid costly respins and chip failures.
Physical and electrical effects at this node challenge both design closure and time to market, and the requirements for design signoff are changing in order to address the inherent manufacturing and process variability. Naturally, this situation can seriously undermine the manufacturability of the design. In fact, a paradigm shift is evident in the all-important signoff analysis step of the digital design cycle.
At issue are the levels of validity and confidence that can be reached with today's IC design closure and signoff methodologies. Designs that pass traditional sign-off standards might still fail in 45-nm silicon. In contrast, using excessive guard-bands or over-conservative margins to satisfy traditional static timing analysis (STA) signoff regimes can negate the benefits that smaller process geometries offer.
This article looks at some of the electrical, physical, and manufacturing challenges to current signoff analysis methods, and shows new ways to improve predictability, productivity and performance at the 45-nm process node. Using these new methodologies, designers can prevent silicon failures and better manage timing, leakage power, and signal integrity " both across a wafer and across the surface of a single chip. By Chin-Chi Teng and Rahul Deokar. (Teng is Engineering Group Director of R&D for the IC Digital Implementation group at Cadence Design Systems, Inc. and Deokar is the product marketing director for Encounter digital IC design.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.