Understanding Clock Domain Crossing Issues
Publication: EE Times EDA Designline
December 24, 2007 -- SoCs are becoming more complex these days. A lot of functionality is being added to chips and data is frequently transferred from one clock domain to another. Hence, clock domain crossing verification has become one of the major verification challenges in deep submicron designs. A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock.
Traditional methods like simulation and static timing analysis alone are not sufficient to verify that the data is transferred consistently and reliably across clock domains. Hence, new verification methodologies are required, but before devising a new methodology it is important to understand the issues related to clock domain crossings properly. Different types of clock domain crossings are discussed here along with the possible issues encountered in each one of them and their solutions. A new verification methodology is then proposed which will ensure that data is transferred correctly across clock domains.
By Saurabh Verma and Ashima S. Dabare. (Verma and Dabare are with Atrenta, Inc.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.