Power-Intent Standards Vie for Designers' Loyalties
Publication: Electronic Design Magazine
February 14, 2008 -- About three years ago, timing closure for large system-on-a-chip (SOC) designs began to develop into one huge headache. Every EDA vendorís toolset had its own interpretation of timing constraints, and there was little or no consistency between those representations. So if you used tools from more than one RTL-to-GDSII vendor, you were in hot water. Designers began clamoring for a single open standard for the modeling of nanometer timing effects, and EDA vendors agreed that a single modeling standard for timing would streamline verification and implementation flows.
The only problem was that the industry did not end up with a single standard for the modeling of nanometer effects. Instead, as is the EDA industryís fractious wont, it served up two: the Effective Current Source Model (ECSM) and Composite Current Source (CCS) models. And while two standards are better than 20, they still arenít as good as one.
Today, a parallel scenario is unfolding, only this time itís in the power domain. Once again, EDA vendors are charting a typically divisive course that will result in multiple standards for the specification of power intent.
Two groups have coalesced, each claiming that it is "user-driven" and giving priority to "interoperability." How they define interoperability, though, may not be to the liking of the design community. So who is behind these two emerging power-intent standards? Why are there two standards and not one? How are they the same, and how are they different? And why might you choose one over the other?
By David Maliniak, Electronic Design Staff Editor
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.