 |
|
New ARC Energy PRO Core Family Slashes Power Consumption By Up to 75%March 11, 2008 -- ARC International has introduced a new family of licensable, 32-bit configurable cores. The ARC Energy PRO core family leverages the company’s recently announced, ultra low power Energy PRO technology to lower power consumption by up to 75%. The Energy PRO family is aimed at the portable and embedded microcontroller markets where lower power consumption is a critical design issue especially in multi-core designs. A new release of ARC’s MQX operating system is included with the new Energy PRO cores, providing additional ability to reduce system-on-chip (SOC) power consumption through monitoring and controlling the SOC’s power by parts other than the core itself. ARC’s new Energy PRO cores use a holistic approach to power reduction that combines hardware and software techniques with a tool chain and libraries. New innovations include architectural clock gating and dynamic voltage and frequency scaling to reduce power usage, which are under the control of a dedicated power management unit. Power control also can be extended to other functional blocks within the SOC to significantly reduce total chip power. By combining the most appropriate energy saving strategies on a per-block and per-subsystem level, SOC designers can define multiple power management modes to ensure that the device uses the minimum possible power while still providing the required performance on a real time basis – even to the extent of shutting the core down when no threads are running. The ARC Energy PRO core familyEach member of the new Energy PRO core family is configured to address a specific application area. The ARC Energy PRO 20 is an ultra-low-power, cache-less CPU/DSP core that is designed for embedded applications including hard real-time controllers, dedicated function blocks and medical devices. Closely coupled, single-cycle memories provide the fast computation and deterministic response required in hard real-time applications. The ARC Energy PRO 30 is an ultra-low-power CPU/DSP core designed to function as a complete processor solution for applications such as portable and mobile appliances, wireless connectivity management and RTOS-based systems. Both cores can take advantage of ARC’s optional advanced modules including ARC XY Advanced DSP, ARC FPX single and dual floating point extensions, and SmaRT real time trace. Energy PRO cores are fully configurable by licensees using ARChitect, ARC’s processor configurator tool. ARChitect produces synthesizable RTL which is compatible with all major industry standard EDA flows. A fully integrated reference design methodology (RDM), based on the Common Power Format (CPF), has been developed with Cadence Design Systems, Inc. It leverages the Cadence Low-Power Solution to reduce power consumption and provides a drop-in solution that improves productivity and reduces time to market. Virage Logic, Inc’s Area, Speed and Power (ASAP) logic low-power standard cell libraries are used in order to demonstrate advanced power savings features such as isolation cells and level shifters. MQX-EP RTOSMQX-EP has been specially designed to complement ARC’s new Energy PRO core family. This new RTOS provides developers with an easy-to-use software interface for system-wide power management, monitoring and profiling, thus enabling Energy PRO’s power saving features to be fully exploited and optimized for deeply embedded, real-time applications. The combination of ARC’s MQX-EP software and Energy PRO processors create a holistic solution. MQX-EP provides an advanced level of software integration with Energy PRO technology, and the resulting power reductions are enabled by the MQX software technology and the MetaWare development tools. This combination of pre-verified hardware, software and development tools equips ARC customers with a complete end-to-end solution. AvailabilityThe new ARC Energy PRO cores and the MQX-EP RTOS are now available for licensing. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |