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How to Overcome the Increasing Management Complexity of FPGA/PCB Pin SynchronizationPublication: EE Times Programmable Logic Designline July 2, 2008 -- Pin and part swapping has long been one of the many techniques that electronics designers exploit to decrease PCB routing complexity and remain competitive. But the accelerated adoption of FPGAs due to their increased affordability and ever improving performance has placed new pressures on traditional PCB design flows. Yesterday's task of exchanging a few gates within an IC package or the connections to a couple of resistor arrays is quite different from today's task of managing several hundred pin swaps across one or more FPGA devices, and then synchronizing those changes with the FPGA design. As the design progresses through multiple iterations, the task of synchronizing the data and pins across the PCB and FPGA domains has become a full-time job in itself and the blessing of pin swapping has become a curse. So, designers need to overcome this increasing synchronization complexity so that they can continue to exploit the benefits of programmable hardware. Through examining traditional design processes and their efficiency at dealing with FPGA-based designs, this article explores the ways in which board-level designers can harness the benefits of FPGAs without being overwhelmed by their complexity. Of particular interest is the management of pin-swapping data across schematic, PCB and FPGA design domains. By Marty Hauff. (Hauff is presently engaged in the writing, design and creation of Altium Designer training videos for Altium, Ltd.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |