 |
|
Building a Configurable Embedded ProcessorPublication: EE Times Embedded September 9, 2008 -- When most design groups think of the term "configurable processing," their minds immediately go to configurable processors offered by IP vendors. But those designers may be overlooking an obvious and trusted alternative: processor-laden FPGAs. Today FPGA vendors offer high performance industry standard MPU cores on board feature-rich FPGAs. By using a mix of FPGA vendor and EDA vendor tools and a bit of ingenuity, embedded designers can extend the instruction set of the processors running in these FPGAs to add their own unique functions to their designs. And they can do so without having to go back to school to get a degree in hardware engineering. Over the last couple of years, FPGA and EDA vendors have made great strides in creating software-to-FPGA tools that will allow embedded designers to effectively use FPGAs to increase the performance of their designs, while meeting timing budgets and cutting bill of material costs. Let's examine a configurable FPGA-based hardware accelerator methodology in which we'll use an auxiliary processing unit (APU) controller interface to integrate co-processing accelerators to vastly speed up a system's overall performance. In particular, we'll employ this configurable FPGA-based hardware accelerator methodology to increase the performance of a machine vision system that formerly employed an embedded processor. By David Pellerin and Dan Isaacs. (Pellerin is Founder and CEO of Impulse Accelerated Technologies and Dan Issacs is Director, APD Embedded Marketing at Xilinx, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |