The Need to Address Power During Manufacturing Test
Publication: EE Times EDA Designline
October 6, 2008 -- Driven by the expansion of wireless and power-efficient devices and by the marketing requirement to deliver 'green' electronic systems, designers are increasingly employing low-power design techniques to manage the growing challenge of functional power dissipation. Until recently, the idea of managing power during manufacturing test has been a secondary concern. But with shrinking geometries and lower voltage thresholds comes an increasing awareness that excessive power consumption during test can have an impact on digital IC reliability, leading to power-driven failures, infant mortality, and false failures at final test. The emergence of these phenomena calls for adoption of specific power management and low power design techniques for manufacturing test.
By Anis Uzzaman, Patrick Gallagher, and Edward Malloy. (Uzzaman is a Senior Product Engineering manager at the Front End Design Group of Cadence Design Systems, Inc.; Gallagher is an architect for the Front End Design Group of Cadence; and Malloy is a Product Marketing Manager for the Front End Design Group of Cadence.)
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