Lattice Enhances Hardened SPI4.2 Solution Portfolio

November 20, 2008 -- Lattice Semiconductor Corp. announced todaythat its LatticeSCM FPGA family-based SPI4.2 MACO (Masked Array for Cost Optimization) cores have been enhanced by adding link layer buffer management options. The LatticeSCM FPGA family has offered feature-rich SPI4.2-based cores and bridge reference designs at the low cost, power and printed circuit board footprint. These new features enhance this solution portfolio by allowing designers the option to use a parameterizable buffer manager for applications needing per-channel bandwidth management.

The LatticeSCM FPGA platform provides designers with multiple hardened SPI4.2 cores using Lattice’s exclusive MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions, developed by Lattice, that shorten end-system time-to-market and lower device cost, power and PCB footprint targets. These new features provide designers with a programmable buffer manager capable of:

Up to 16 separate physical FIFOs per TX/RX direction Packet over-flow and error drop Both store and forward as well as cut-through operation Parameterizable buffer depth and thresholds Dynamic channel provisioning Programmable sequencer-based scheduler

Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
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