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Unified TLM 2.0 Coverage MeasurementCompany: JEDA Technologies, Inc. In OSCI’s Transaction Level Modeling, draft-2 (TLM-2) based Virtual Platform (VP) development an environment, debugging is a time consuming and expensive effort today, especially when problems are caused by models that represent hardware. For production application, end users demand high-quality models and platform targets along with advanced analysis capabilities into this system. In this paper we present one approach for quality measurement at model level and platform level. At platform level, by collecting and analyzing software’s interaction with the TLM 2.0 based models, or the model responses to system level traffic during architecture exploration, one can easily measure certain aspects of simulation coverage for advanced analysis purposes. At model level, SystemC code coverage provides the very basic means for quality control. Using the newly released OSCI TLM2 examples, real coverage data are collected and analyzed to identify coverage holes. | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |