SilTerra Ready for 110-nm CMOS Logic Technology Pilot Production
March 26, 2009 -- SilTerra has officially debut the industry foundry-compatible copper-based 110-nm logic technology as the 10% optical shrink for it's copper-based 130-nm CMOS logic technology, which has been in mass production for more than 2 years. The technology, code name CL110G, applies 10% linear optical shrink on customer 130-nm databases. The electrical device specification and Spice model of CL110G are optimized to match with the original 130-nm design. The CL110G technology is developed with advanced processing tools to enhance yield performance.
"Customers could take advantage of the new CL110G platform to squeeze extra dies per wafer with uncompromised device performance. Customers will gain about 19% of extra die per wafer with reference to the pure digital 130-nm CMOS logic design. CL110G is now ready for customers' prototypes. I
Silterra's CL110G technology is optimized for high-performance and high-density designs with demanding product performance. This technology features eight layers of dual damascene copper metallization, borderless contacts and vias with FSG inter-metal dielectric. The technology is supported by a complete set of foundry foundation intellectual property (IP) from Virage Logic, ARM and other silicon IP providers to help shorten time-to-market and reduce development cost. The design flow is also validated in Synopsys and Mentor Graphic platforms.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.