Synopsys Launches IC Validator, Offers Significant Reduction in Physical Verification Turnaround Time for Advanced Designs
May 13, 2009 -- Synopsys, Inc. has announced the IC Validator DRC/LVS solution for in-design physical verification and signoff for advanced designs at 45nm and below. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity. IC Validator can significantly reduce total physical verification time through in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores. IC Validator is production ready, having been included by TSMC for the company's EDA qualification program of design rule checking/ layout verification signoff (DRC/LVS) starting from 28nm.
"TSMC employs rigorous qualification criteria to help ensure DRC/ LVS accuracy for signoff physical verification. We have worked closely with Synopsys during the development of IC Validator and have included it in our 28-nm EDA qualification program," said S.T. Juang, Senior Director of Design Infrastructure Marketing at TSMC. "Such a collaboration with Synopsys has produced good results with IC Validator in TSMC's most current physical verification EDA qualification report."
Prevailing approaches to physical design today can be described as 'implement-then-verify,' says Synopsys, and result in multiple iterations between design and signoff. At leading-edge nodes such as 45nm and below, the implement-then-verify approach can be slow and may complicate convergence as layout corrections can alter design objectives such as area, timing, and power. In-design physical verification brings the full physical verification constraints into the design phase, helping to ensure clean layout upon leaving the design environment and avoiding late-stage surprises close to tapeout. With in-design verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.
In addition, IC Validator can automatically discover and fix design rule violations within the global context of the design. Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. Working in concert with IC Compiler, IC Validator's in-design flow dramatically reduces such iterations by performing signoff-quality, timing-driven metal fill during the design phase.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.