A 0.79-mm2 29-mW Real-Time Face Detection IP Core
Publication: Design & Reuse
May 25, 2009 -- A 0.79-mm2, 29-mW real-time face detection IP core is fabricated in a 0.13-mm CMOS technology and its performance was evaluated. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface. Comprehensive optimization in both algorithm and hardware design improves performance and reduces area and power dissipation. Two kinds of templates with facial features are proposed to achieve high speed and yet accurate face detection. A Steady State Genetic Algorithm is employed for high-speed hardware implementation of template matching. To reduce area and power dissipation, frame memory is optimized at minimum and the detection engine is shared for two kinds of template matching. The IP core can detect 8 faces per frame at 30fps. Face detection accuracy is 92%.
By Yuichi Hori, Yuya Hanai and Tadahiro Kuroda. (All are with Keio University, Yokohama, Japan)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.