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Power vs. Performance: The Ultimate DSP Design ChallengePublication: DSP-FPGA June 15, 2009 -- For years, DSP designers have tackled the task of providing high-performance chips, in a small footprint, with maximum flexibility and software programmability. Recently, the pace of performance improvement has slowed at the same time as new more complex applications have evolved. To bridge the gap, high-performance multicore DSPs are increasingly being used in telecommunications access, edge, and infrastructure equipment to process voice, video, and radio signals. Even with the advent of multicore DSPs, power dissipation challenges are limiting their ability to address a complete solution from a density, cost, and power perspective. To meet product requirements, telecommunications equipment manufacturers have necessarily turned to combinations of DSPs and application specific integrated circuits (ASICs). This trend conflicts with the need for upgradable solutions for access and infrastructure equipment that must last many years in network deployments. ASICs are not as flexible or field-programmable as a DSP, but they can be significantly more cost- and power-efficient. For DSPs to achieve the required performance and efficiency the issue of power dissipation must be overcome. By Doug Morrissey. (Morrissey is Vice President and Chief Technology Officer at Octasic, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |