Hitachi Achieves 40% Reduction in PCB Place-and-Route Design Time with Cadence Global Route Environment
June 30, 2009 -- Cadence Design Systems, Inc. today announced that the Cadence Global Route Environment (GRE) technology for Cadence Allegro PCB design enabled Hitachi, Ltd. to successfully reduce printed circuit board (PCB) place-and-route design time by 40% for a high-speed communication product. Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available.
"High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common," said Toru Hiyama, General Manager, Monozukuri Innovation Operation, Hardware Monozukuri Division at Hitachi. "In order to complete the design in the shortest cycle time possible while maintaining high quality, it was critical for us to solve the bottleneck of place-and-route for PCBs. By using Cadence GRE technology, we can solve the routing bottleneck as well as enhance the reliability of the design."
The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCBs. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process it lets users plan the routing strategy at a high-level through Interconnect Flow Designer. Through the Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints. In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach becomes very effective for memory interfaces such as DDR2, DDR3, and serial interfaces such as PCI Express and PCI Express Gen II with their stringent high-speed design constraints.
At Hitachi, automatic routing had not previously been available to route signals with high-speed constraints. The GRE technology dramatically improves the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths. With GRE, Hitachi was able to effectively manage PCB designs with various tradeoffs. Hitachi expects further reduction of design time as the GRE performance and features are updated and further enhanced.
In addition to the full-constraints routing capability, Hitachi said the GRE technology will be effective for many other PCB design challenges, such as engineering changes and routing estimation. Hitachi plans to deploy and promote the GRE technology as a standard solution throughout the design environment.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.