Emulation Finds Its Role
Contributor: Emulation and Verification Engineering (EVE)
July 15, 2009 -- Itís taken 25 years or longer, but Iím here to report that emulation platforms finally have become the key component to almost all engineering teamsí verification flows. Itís about time, wouldnít you say? After all, verification accounts for 70% or more of the development cycle. And that percentage could go higher as the semiconductor industry embraces multicore architectures, moves to smaller process technologies and increasingly relies on embedded software content in chips.
The push to system-on-chip (SOC) design is accelerating and, with it, the uncertainty about how to debug the embedded portion of the system. Software is a new and growing concern and co-verification strategies are part of most project planning. Engineering teams have turned to reliable, but unglamorous, emulation because, among other reasons, it provides an all-in-one system for hardware debugging and embedded software validation.
Yes, emulation platforms have found a role in the war on complexity. They have proved invaluable because hardware designers and software developers can share the same system and design representations. Formerly dissimilar parts of an engineering team now can work together to debug hardware and test the integration within an SOC of software and hardware before first silicon.
Itís been a long, rough and hard-fought battle to win over engineering teams who first began using emulation to supplement software simulation in the 1980s. Theyíve been treated to older generations of emulators that were difficult to use and the prohibitive cost limited adoption to only those with big budgets and monumental challenges. Any engineer living through those early days can hardly forget the "time to emulation" refrain.
Rapid prototyping based on off-the-shelf field programmable gate arrays (FPGAs) and offered by both large and small vendors has had a modicum of success, but has suffered heavy competition from internal development, well known as roll-your-own (RYO). Due to limited software support that complicates the process of mapping a design onto an array of FPGAs ó and, therefore, often viewed as a crude emulator ó rapid prototyping is best used on small to medium designs with fewer than six to nine FPGAs.
Perceptions are changing, along with capabilities and usability. Engineering teams consider emulation platforms as a necessary tool for accelerating verification testing because it helps them to plan more strategically and implement a debugging methodology based on multiple abstraction levels. These days, emulation platforms are much more cost-effective and are invaluable when the task calls for executing billions of verification cycles; another reason why adoption rates are growing. They run faster and are easier to use as well.
Thatís not to say that even todayís highly sophisticated emulation platform is a plug-and-go system. To be effective, it needs a software-aware debugging environment that tracks a bug in hardware coming from the software debugger. This way, a design problem can be traced across the boundary between embedded software and hardware to determine whether the problem lies in the software or in the hardware. Otherwise, itís almost impossible to identify the root cause of the problem.
Starting from a database of several billion clock cycles, a software debugger can help to quickly localize a problem to within a few million clock cycles. By using checkers, monitors and SystemVerilog Abstractions (SVAs), the engineering team can switch from tracking a problem in the embedded software to chasing a problem in the underlying hardware to narrow down the area of concerns to a few thousands clock cycles. At this stage, traditional waveform analysis can accomplish the task of finding the bug. To recap, the ability to work at various abstraction levels starts with embedded software and moves to lower levels of abstraction, tracing the behavior of individual hardware elements along the way.
Engineering teams are adding emulation platforms to their verification flow because they are fast, affordable, easy to use and can execute billions of verification cycles in a short period of time, a requirement for embedded designs.
Fortunately, the story of emulation product development and refinement is an unusual one because it normally doesnít take 25 years for an EDA product to mature or, more important, find a role. In any case, emulation platforms have finally arrived to become a valued component of hardware/ software co-verification strategy.
By Lauro Rizzatti.
Lauro Rizzatti, general manager of EVE-USA, has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing, and engineering.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.