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The Best of Both Worlds: Optimizing OCP Slave Memory BehaviorPublication: EE Times EDA Designline November 9, 2009 -- Verification IP for OCP is generally used to achieve one of two main verification objectives; at the module level to test OCP components and their interfaces; or at the bus fabric level when some or all of the components may be replaced by the verification IP to test the behavior of a system. In either case, the VIP behavior used in verification will ultimately be replaced with a real component or interface, and so it is important that the verification IP can represent the behavior of the real component or components; even better to represent a spread of components that might be used in conjunction with the design being tested. The real slave components in an OCP design will have memory of one form or another and so accurately modeling the behavior of the memory in the verification IP can be critical to understanding system performance and identifying potential hazards. By Neill Mullinger. (Mullingergroup marketing manager at Synopsys, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |