Boundary Scan and JTAG Emulation Combine for Advanced Structural Test and Diagnostics
Publication: EE Times Embedded
November 10, 2009 -- While continuously improving IC and SOC technologies, higher clock rates, and more powerful processors are music to the design engineers' ears, the headaches of test engineers are getting worse and worse. The ever decreasing test access was the worrying factor in the past, but a new problem arose in recent years with the dramatically increasing speed of the signal transmission.
The resulting failure phenomena and test access limitations have an inevitable impact on the efficiency and practicality of test strategies.
It is apparent that structural tests for detecting connectivity faults (opens and shorts) have huge advantages regarding test automation, diagnosis, and deterministic fault coverage. However, test coverage for dynamic failure phenomena demands higher test speed in order to carry out at-speed tests.
For this, functional tests are more suitable, although test development effort is enormous and failure diagnosis is rather limited. A single test technique that meets all requirements is neither existent nor on the horizon. Instead a suitable mix of techniques is the way to go. The combination of boundary scan and emulation test can be considered as a particularly interesting approach.
By Heiko Ehrenberg and Thomas Wenzel. (Ehrenberg is president of GOEPEL electronic GmbH and Wenzel is Managing Director of the JTAG/coundary Scan division at GOEPEL.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.