Low-power LDPC Decoder Created Using High-Level Synthesis
Publication: EE Times EDA Designline
January 13, 2010 -- With the popularity of mobile wireless devices soaring, the wireless communication market continues to see rapid growth. However, with this growth comes a significant challenge. Many applications, such as digital video, need new high data rate wireless communication algorithms. The continuous evolution of these wireless specifications is constantly widening the gap between wireless algorithmic innovation and hardware implementation. In addition, low power consumption is now a critical design issue, since the life of a battery is a key differentiator among consumer mobile devices.
The chip designer's most important task is to implement highly complex algorithms into hardware as quickly as possible, while still retaining power efficiency. High Level Synthesis (HLS) methodology has already been widely adopted as the best way to meet the challenge. This article gives an example in which an HLS tool is used, together with architectural innovation, to create a low power LDPC decoder.
By Yang Sun, Joseph R. Cavallaro and Tai Ly. (Sun and Cavallaro are at Rice University, Houston, Texas, and Ly is with Synfora, Inc.)
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