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Enabling Assertion-Based VerificationCompany: Zocalo Tech, Inc. Assertions are properties or facts describing the required and forbidden behavior of a design. They are "executable specifications" that are monitored during simulation by assertion checkers included in the design file. SystemVerilog to include Assertion Based Verification (ABV) is viewed as the evolving standard that can have major impact on reducing verification time and cost. Various studies have shown that using ABV can reduce debug, now representing 60% of the functional verification time and cost, by 50%. In spite of the promise of ABV, wide scale use has not materialized. ABV is a difficult technology to implement and is perceived as marginally cost effective. If it were easy, everyone would have adopted it by now. The objective of this paper is to:
Key to this paper is the difference in the terms "Using Assertions" and "Assertion Based Verification." Using Assertions is an ad hoc process dependent on the skill and desire of the designer or verification engineer to provide assertions as part of the functional verification process. Assertion Based Verification (ABV) is a systematic methodology requiring the use of assertions in the functional verification flow and the infrastructure to control and manage them. Most surveys on using ABV reflect assertion use as opposed to ABV. We believe terminology is a problem that confuses the issue. This paper focuses on simulation based functional verification, the standard for chip verification. However, formal verification is dependent on assertion technology and has the same set of issues that are becoming apparent as formal technology matures and becomes more widespread. | |
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