FPGA Compilation On-Site or In the Cloud
Publication: EE Times Programmable Logic Designline
August 9, 2010 -- It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon. Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs — compilation time.
By Rick Kuhlman. (Kuhlman is an Embedded Software Product Manager for National Instruments Corp.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.