Avago Technologies First to Demonstrate 28-Gbps Performance With 40-nm SerDes
November 2, 2010 -- Avago Technologies, Ltd. has demonstrated 28-Gbps serializer/ deserializer (SerDes) performance in 40-nm CMOS process technology. The milestone equates to higher bandwidth ASICs that integrate the SerDes intellectual property (IP), increasing the speed of data communication for servers, routers and other networking, computing and storage applications.
Avago SerDes cores can be easily integrated due to their modular, multirate architecture. Avago is able to integrate more than 200 SerDes channels or over 190 million gates on a single ASIC, with FET counts routinely in excess of 4 billion. The SerDes cores offer unique decision feedback equalization (DFE), resulting in lower overall power usage. Additional key differentiators include best-in-class data latency, noise immunity, jitter, and crosstalk performance.
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.