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Choosing an Effective Embedded SOC ASIC Design StrategyPublication: EE Times Embedded December 13, 2010 -- In large and complex system-on-chip ASIC design, two of the most challenging tasks are those involving design closure, timing routing and power. It is a tedious task to converge on timing and routing, owing to the limitations of design size and the memory-intensive calculations. Essentially, it is dependent on the design size that an EDA tool can handle. In such cases, it is advisable to go for a hierarchical approach instead of a flat top. Generally, the blocks are demarcated on the basis of functionality, backward compatibility, third-party IP, etc. This article details the difference in terms of runtimes, routing congestion, timing summary and utilization for a design that is done as hierarchical vs. the same design using the flat approach.
By Sunit Bansal. (Bansal is a Senior Design Engineer at Freescale Semiconductor, Inc.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |