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Evolution of Manufacturing Closure for Advanced Nodes: Part 2Publication: EE Times EDA Designline February 28, 2011 -- Starting at the 40/45-nm design node, DRC/DFM closure emerged as a significant new challenge to IC designers. No longer could manufacturing concerns be effectively handled with the traditional design-then-verify flow. This trend is expected to continue and worsen at the 32nm and 22nm nodes, where manufacturing closure may become a serious bottleneck in design schedules. The reasons behind the growing difficulty of manufacturing closure are explored in Part 1 of this series. The traditional flow, which consists of completing the physical design before performing physical verification checks and DFM improvements, is based on a key assumption — that the place-and-route tool can get close enough to make physical sign-off predictable. In the past, this was a reasonable assumption and the methodology worked. But at sub-40nm it begins to break down as the previous generation routers are not designed to handle the many new and complex DRC/DFM rules.
By Ivailo Nedelchev and Sudhakar Jilla. (Nedelchev and Jilla are with Mentor Graphics Corp.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |