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Planning Reset Strategy: Flow and Functionality in OVCPublication: EE Times EDA Designline March 9, 2011 -- Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/ system and is the first step in the sequence of operations done for any system bring up. The following article addresses this essential strategy to be followed during verification using an OVM-based testbench. While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
By Parag Goel and Pushkar Naik. (Goel is a Senior Design Engineer and Naik is a Principal Design Engineer at AppliedMicro Corp.) | |
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information. | |