Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment
Publication: Design & Reuse
March 17, 2011 -- The article describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high-speed simulation, early software development and early testbench creation.
The described verification environment, based on SystemC methodology, has been used in the process of functional verification of the both models. The work presents how such multi-model (RTL/TLM) design can be created and verified in configurable, multi-layered and coverage-driven verification environment with third-party verification components.
By Ireneusz Sobanski and Wojciech Sakowski. (Sobanski is with Evatronix SA and Sakowski is with the Institute of Electronics, Silesian University of Technology.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.