The Traditional Approach to IC Implementation and Its Problems
Publication: Electronic Design Magazine
March 11, 2011 -- Throughout the history of the IC industry, each scaling advance to a new process node has presented a raft of new challenges. In the recent past, relatively straightforward spacing, width, and overlap rules might be tightened up a bit at each node, but in general, these rules did not impact design styles to any large degree. However, at 45nm and below there are many, many more challenges than we have seen moving from technology node to technology node.
As geometries continued to shrink to well below the lithography exposure wavelength, the interactions between layout features (shapes) became more important and more complicated. This has led to more complex design rules and more complex verification checks to ensure manufacturability.
No longer is it sufficient to observe simple one-dimensional spacing and width rules. Increasingly, systematic manufacturing defects result from the interaction of multiple shapes and their relative position within a context window or area of interdependence. It has become necessary to evaluate complex geometrical functions in multiple dimensions, to identify specific "problem" layout patterns, to measure the effects of chemical mechanical polishing (CMP) on planarity across multiple layers, and to extend checking into the electrical realm, looking at potential electrical interactions in addition to physical ones.
By Michael White. (White is the Senior Product Marketing Manager for Mentor Graphics Corp's Calibre Physical Verification products.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.