Analyzing Multithreaded Applications: Identifying Performance Bottlenecks on Multicore Systems

Publication: EE Times Embedded
Contributor: Freescale Semiconductor, Inc.

April 7, 2011 -- Various aspects preventing applications from achieving theoretical maximum utilization of multicore resources include: operating system (scheduling, synchronization, etc.), application code (parallelization factor, data/function decomposition, etc.), and hardware architecture scalability (cores, memory subsystem, interconnects, etc.).

We use various multithreaded execution scenarios generated through EEMBC's Multibench as stimulus. We introduce a step-by-step methodology to analyze these scenarios and identify the bottlenecks. Techniques used for kernel tracing, time/ function profiling, etc. and tools used to deploy the methodology are discussed next. The article ends with discussion of various case studies representing different bottlenecks.

By Nandan Tripathi and Amrit Singh. (Tripathi is a senior design engineer at Freescale Semiconductor, Inc. and Singh is a design manager working at Freescale Semiconductor.)

Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.
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