Automating Design Rule Waivers in SOC IP Reuse
Publication: Design & Reuse
March 31, 2011 -- Intellectual property (IP) reuse, especially at the physical IP level, is a key component of the growing system-on-chip (SOC) ecosystem. However, with the increase in the amount and scope of custom and third-party IP integrated into large SOCs, design teams are finding that, far from reducing the SOC verification burden (which is touted as one of the tenets of successful IP reuse), IP integration is actually increasing their workload and slowing down the physical verification process.
Third-party physical IP (which has presumably been silicon-proven) routinely includes design rule waivers, which are negotiated for physical and electrical verification errors that do not significantly affect manufacturability or performance. Intelligent use of such waivers can not only reduce the time for physical layout verification checks (DRC, ERC, LVS), but more importantly, reduce the manual burden of checking every error at the SOC level for compliance with the foundry rules. Since layout verification is, by definition, the last stage of the tape-out flow, reducing the manual effort of error validation by using an automated waiver solution significantly reduces the time-to-market of the SOC.
This article describes an automated waiver-processing methodology and implementation that is accurate and efficient, and can significantly reduce debug tasks and time. The proposed method includes all waiver types commonly encountered, and provides designers and verification teams a degree of customizable control to waive an error only under certain contexts and constraints, which can vary for different errors, designs, or IP. The proposed method automates waiver handling for multiple file formats, supports DRC, ERC, and mask-density type checks, and encapsulates the waiver information with the design IP for easy design management. The method also supports checksum for waiver shapes to guard against inadvertent modification of design layout or waiver shapes.
By Sandeep Koranne and Anant Adke. (Koranne and Adke are with Mentor Graphics Corp.)
Reprinted from SOCcentral.com, your first stop for ASIC, FPGA, EDA, and IP news and design information.